Packaging Technologies
Interaction between a semiconductor circuit and its package can significantly affect product performance. Critical characteristics of the package include the ability to dissipate heat, and to withstand vibration, shock, high temperature, high humidity, and other environmental conditions. Our packaging portfolio continues to evolve to meet the demands for more highly integrated products with smaller footprints, thinner profiles, and more input/output pins per package.
General Package Information (PDF)
Package Application Notes (PDF)
|
Package Style |
Package Designator |
| DFN, QFN |
Micro Leadless Chip Carrier |
EC, EE, EH, EJ, EK, EL, ES, ET, EU, EV, EW, and EX |
| DIP |
Plastic Dual In-Line |
A, B, and M |
| PLCC/PQCC |
Plastic Leaded Chip Carrier |
EA, EB, ED, EP and EQ |
| LQFP |
Plastic Low-Profile Quad Flatpack |
JP |
| TQFP |
Plastic Thin Profile Quad Flatpack |
JS and JU |
| SIP |
Plastic Single In-Line |
K, KA, KB, KN, KT, U and UA |
| SOIC |
Plastic Small Outline Package |
L, LA, LB, LC, LJ and LW |
| MSOP, QSOP and SOT |
Plastic Small Outline Packages |
LF, LH, LQ, LT, LY and LZ |
| TSSOP |
Plastic Thin Shrink Small Outline Package |
LD, LE, LG and LP |
| PMCM™ |
Power Multi-Chip Modules |
W, WH, WV, Z |
|
Plastic Biased |
CA, CB, SA, SB, SE, SG, SH and SJ |