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High-Performance Power and Hall-Effect Sensor ICs

ACS755 Current Sensor IC Frequently Asked Questions ....

What are the differences between the various members of the ACS755 family?

The only functional differences are the mV/A sensitivities of each version.

Although the datasheet for the 200 A version does not show the –PFF package configuration (bent signal and primary conductor leads), which is shown on the other datasheets in the family, it can be provided if desired. The –PFF configuration was not included because currents that high are typically not carried in PC board traces. Contact your local Allegro Sales office for more information.

How is the CB package different from the CA package used in the ACS750 and 752 families?

Externally the packages are identical and have the same footprint. Internally, the CB package leadframe has greater cross-sectional area where it passes the Hall effect element. As a result, the CB package has a resistance of only 100 µΩ, versus 130 µΩ for the CA package.

Can the ACS755 family be applied to both DC and AC currents?

The ACS755 family uses Hall effect technology, which is compatible with electrical currents having both DC and AC components. There is usually a phase lag of at least 45º on the output for AC currents at frequencies exceeding the bandwidth specified in the datasheet.

What does "ratiometric" mean?

This feature is particularly valuable when using the ACS755 with an analog-to-digital converter. A/D converters typically derive their LSB from a reference voltage input. If the reference voltage varies, the LSB will vary proportionally. The ratiometric feature of the ACS755 means its gain and offsets are proportional to its supply voltage, VCC. If the reference voltage and the supply voltage for the ACS755 are derived from the same source, the ACS755 and the A/D converter will both track those variations, and such variations will not be a source of error in the analog-to-digital conversion of the ACS755’s output.

What external components are required?

Allegro recommends the use of a 0.1 µF bypass capacitor between the VCC pin and the GND pin. The capacitor should be located as close as practical to the ACS755 package body.

Is there any way to adjust the gain of the ACS755?

No, the ACS755 sensitivity and 0-ampere quiescent voltage level are programmed at the factory.

How small of a current can the ACS755 resolve?

Without filtering, the ACS755's 100 A version can resolve a change in current level of ≈2.5% of full scale, at 25ºC, through its primary conductor leads. At these levels, the amount of magnetic field coupled into the linear Hall Effect IC is just above its noise floor. However, depending on the temperature, 0-ampere offset error, and the DC current level, the percentage error of the current sensor IC output will often be greater than this minimum resolvable current. Resolution can be improved by filtering the output of the ACS755. Up to a threshold value, this can be done without limiting the response time. See the application note "Managing Noise Levels in the ACS75X Current Sensor ICs," at www.allegromicro.com/en/Products/Design/an/acs75xan1.pdf.

What is the ESD tolerance of the ACS755?

Typical ESD tolerance is 6 kV human body model, 600 V machine model.

Can Allegro bend the leads under the package or outward, so that I can surface-mount the ACS755?

In order to safely conduct 200 A currents, the power leadframe in the ACS755 has been constructed with a relatively heavy gauge. Because of this heavy gauge, the terminal leads are not very flexible. If the ACS755 is surface-mounted, small amounts of board flex, or the action over time of thermal expansion and contraction, would break the IC off the board. Allegro does not believe surface-mounting is practical for this device.

How should I solder the ACS755 onto my board?

To ensure a robust joint to the board, Allegro recommends adding a ring of through-holes in the solder pad area around each of the two broad primary conductor leads that carry the current being sampled. These holes are shown in the diagram in the FAQ "Do you have a recommended footprint for the ACS755 (CB package)." General soldering recommendations for the CA and CB packages have been added to the application note "Soldering Methods for Allegro Products (SMD and Through-Hole)," which is on the Allegro website at www.allegromicro.com/en/Products/Design/an/an26009.pdf.

How should I connect to the straight-leaded package configurations?

Allegro recommends a tin-fusing welding technique. This method is described in our application note Guidelines for Designing Subassemblies Using Hall-Effect Devices.

Do you have a recommended footprint for the ACS755 (CB package)?

Yes, the following shows the recommended footprint for the –PFF configuration.

ACS755 Solder Pad

The portion (A) of the above footprint, the three small through holes for the signal pins, also applies to the –PSF configuration (which has straight primary conductor leads).

Can I get the Gerber files for your evaluation board?

Yes, download from:
http://www.allegromicro.com/en/Products/Part_Numbers/0755/Allegro_CA_CB_EvalBoard.zip.

I can't use Gerber files; is any other format available?

Yes, an AutoCAD 2004 .DXF file can be downloaded from:
http://www.allegromicro.com/en/Products/Part_Numbers/0755/Allegro_CA_CB_EvalBoardDXF.zip.

The copper areas are defined as "regions" in these files.

How thick are the copper traces on your evaluation board?

The evaluation board uses 4 oz. copper.

Are there any other design guidelines for applying the ACS755?

Care should be taken to minimize the inductance of the current path to be measured. Also, attention should be paid to minimizing the contact/connection resistance of any connections in that path.

What is the inductance of the ACS755 (CB package)?

Typical measured inductance versus test signal frequency are:

  • 32 nH at 10 kHz
  • 24 nH at 100 kHz
  • 21 nH at 200 kHz

Does the ACS755 contain lead?

No, the ACS755 family is lead-free. All leads are plated with 100% matte tin, and there is no lead inside the package.

What is the high-current leadframe made of?

The heavy gauge leadframe is made of oxygen-free copper.

How susceptible is the ACS755 to stray magnetic fields?

The ACS755 contains a concentrator core that acts not only as a concentrator of the flux lines generated by IPRIMARY, but also as a shield to protect the sensor IC from ambient common-mode fields (typical rejection of common mode fields is –41 dB). The results are detailed in the following chart, which compares the output voltages, VOUT, of an unshielded linear Hall effect sensor IC and that of the ACS755. The devices have the same gain, and are exposed to the same magnetic field, applied in an air core through the top of the package.

ACS755 External Field Effects

What safety certifications does the ACS755 have?

The ACS755 family also has been certified by TÜV America to the following standards:

  • UL 60950-1:2003
  • EN 60950-1:2001
  • CAN/CSA C22.2 No. 60950-1:2003

The mold compound is UL recognized to UL94V-0.

What happens if I try to drive more than the specified 10 nF maximum capacitance with the output of the sensor IC?

The output of the sensor IC may oscillate.

What happens if I try to drive less than the specified 4.7 kΩ minimum resistance with the output of the sensor IC?

The sensor IC may not produce an output, as its output driver will not be able to supply sufficient current.

What is the overcurrent tolerance of the ACS755 devices?

Because of its low, 100 µΩ internal resistance, the overcurrent capability of the CB package of the ACS755 sensor IC is highly dependent on the characteristics of the bus bar or printed circuit board on which it is mounted. In the case of a PCB mounting, trace width and thickness, the number of layers, the presence or absence of ground and/or power planes, and the gauge of the cables that carry the current on and off the board are all significant factors. It is also dependent on the maximum operating temperature of your application and the frequency with which the overcurrent occurs.

By way of example, we have characterized the ACS755 devices on the Allegro ACS755 evaluation board, connected to the current source with 2 AWG cables. This a 2-layer board with 4-oz. copper. (For drawings and Gerber files, see the FAQs: Can I get the Gerber files for your evaluation board? and I can't use Gerber files; is any other format available? on this page.) The results are provided in the following table.

Tested Maximum ACS755 Overcurrent Levels and Durations
Applicable to devices on Allegro ASEK 755 evaluation boards connected with 2 AWG cables
Ambient Temperature
(°C) 		Maximum Current
(A)
10 s, 10% Duty Cycle, 100 pulses applied
25 350
85 350
150 260
3 s, 3% Duty Cycle, 100 pulses applied
25 450
85 425
150 375
1 s, 1% Duty Cycle, 100 pulses applied
25 1200
85 900
150 600

How will capacitive coupling between the current path in the ACS755 and the Hall element effect the device output?

The power supply rejection test is conducted by injecting a high-frequency sinusoidal frequency onto the high-current leads. The signal coupling onto the output of the Hall effect device is then measured. The ACS755 family devices exhibit a high level of power supply rejection as the following table, of typical capacitive coupling of a 20 V peak-to-peak signal on the current path, reveals. In addition, the chart following the table indicates performance as a function of frequency.

Noise Frequency
(MHz) 		Passed-Through Signal Magnitude
(mv/20 V) 		Attenuation
(dB)
10 720 –28.9
5 430 –33.3
1 50 –52.0
0.5 48 –52.4

ACS755 Capacitive Coupling

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