Techniques for Mitigating Interference While Measuring High Frequency, High Current Transient Responses

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By Maxwell McNally and Ryan Dunn,

Allegro MicroSystems, LLC



This application note will demonstrate techniques on how to avoid coupling the field from high-current transients onto the signal and power lines of current sensors in order to avoid a perceived distortion of the output. Along with creating transient fields, the circuitry used to create current steps can change its power draw quickly, which may disrupt power to a device. The related Power-On Reset event and the wave forms that indicate this event will be explored.


Figure 1: Poor setup allowing coupling onto VCC

Figure 1: Poor setup allowing coupling onto VCC
[1]: Scope Probe
                                                                             [2]: Current Injection Board (arrows indicate current direction)
                [3]: Current Monitor Probe
            [4]: VCC and Gnd Leads


Figure 2: Poor setup output ringing

Figure 2: Poor setup output ringing



When taking measurements in a laboratory with switching equipment, it is important to take care so that high frequency signals do not couple field onto signal or power wires. Wires that run close to switching circuitry or high current traces,especially if in a loop, are often places of concern where magnetic fields may couple and cause measurement error.This can lead to ground bounce, changes in supply voltage,current injection, and other phenomena which may change the apparent performance of a device.Switching equipment is used to create an input current step to test the response time or sensitivity of current sensing devices.Coupling is a concern when working with current steps created by large capacitor banks. When they begin to charge or discharge, the capacitor banks can instantaneously spike their current draw, which can temporarily change the voltage at the VCC or Gnd node. If for any reason the supply voltage to the part is reduced enough, the part may reset. Detecting this behavior is difficult. The reset can appear on either edge of the current step and the output may not discharge immediately,depending on the load capacitance.

Lab conditions can be cramped, often with little room to separate equipment and devices being tested. It is important to take care to distance switching equipment from test leads as well as devices while taking measurements. Running the power leads away from the switching of the current injection board eliminated the ringing on the output of the device inthis experiment. Figure 3 shows the leads taped away from the current injection board and Figure 4 shows the resulting clean signal overlaid upon the ringing signal.The small change made by moving the wires away from the current injection board completely eliminated the ringing.Allegro recommends twisting together VCC and Gnd away from any power circuitry to reduce inductance and avoid coupling.



Figure 3: Clean setup minimizing coupling onto power wires of the device

Figure 3: Clean setup minimizing coupling
onto power wires of the device


         Figure 4: Clean trace overlaid with ringing trace

Figure 4: Clean trace overlaid with ringing trace



Output Undershoot Due to Current Transients


In the second laboratory setup, a single inline package (SIP)device was used to demonstrate an undershoot condition. When the Gnd and VCC clips were connected parallel to thebus bar, as shown in the picture on the left in Figure 5, it allowedfor the maximum coupling of magnetic field onto the clips. Thepicture on the right in Figure 5 shows the clips perpendicularto the bus bar, which minimized field coupling. A dramaticdifference was observed on the output after this change wasmade. Bringing the clips perpendicular not only mitigated thisundershoot seen in Figure 6, but Figure 7 shows that ringing hasalso been removed. Note that neither the gain of the device northe scope scaling was changed between Figure 6 and Figure 7,only the offset to capture the whole undershoot.



Figure 5: A1367 high coupling setup (left) and low coupling (right)

Figure 5: A1367 high coupling setup (left) and
low coupling (right)


Figure 6: Parallel setup with significant undershoot and ringing

Figure 6: Parallel setup with
significant undershoot and ringing 

  Figure 7: Perpendicular setup with minimal undershoot and ringing

Figure 7: Perpendicular setup with
minimal undershoot and ringing



Power-On Reset events due to VCC Chopping


A third experiment highlights a scenario involving fast switchingof capacitors to generate a high-speed current transient. Thesehigh-current transients have been seen to couple onto thesystem’s supply voltages and create disturbances on sensors andmicroprocessors. This can cause VCC and Gnd to fluctuate, whichwill disrupt the device, as seen in Figure 8. Extreme situationsmay cause VCC to drop low enough to cause a Power-On Reset(POR) condition; the device will repower due to VCC droppingtoo low for too long. This VCC disturbance can be fast—less than100 ns—and still cause a reset condition. Bypass capacitors helpprevent VCC from fluctuating quickly; however, this is a resultof the setup or layout chopping VCC, not an issue with the partreacting to a step response.



Figure 8: Device resets from VCC pulled low briefly

Figure 8: Device resets from VCC pulled low briefly

Figure 9: Part output during slow VCC ramp

Figure 9: Part output during slow VCC ramp


While the part resets, the output enters high-impedance mode.The datasheet for an individual part will specify the Power-OnReset thresholds. POR has two thresholds: rising VCC (VPORH)and falling VCC (VPORL). Figure 9 shows the output of a partresponding to these thresholds, first becoming underpoweredwhen VCC falls below VPORL, and then powering back on as VCCrises above VPORH. 

If a load capacitor is used, the output may appear to slowlysettle when the device enters high-impedance mode. Thisstrange behavior can appear to be unrelated to the switching,happening on the down stroke of the current input. In Figure 10,the discharge of the device with and without load capacitorsis shown in a VCC chop event. The output quickly drops toground without a load capactitor, whereas with a 1 nF capacitor,the output only discharges halfway. These two waveforms areindicative of a Power-On Reset event. The output is pulled lowwhen the device begins to turn on.

These profiles match with a normal power on and off condition,like those seen in Figure 11. First, any charge stored on thecapacitance of the output pin discharges. The output then spikeshigh when power is restored to the part. Finally, the output pullslow before rising to normal operation.


 Figure 10: Capacitor discharge as part resets

Figure 10: Capacitor discharge as part resets 


Figure 11: Normal power on and power off functionality

Figure 11: Normal power on and power off functionality




There are many situations in which an inadequate test setupmay cause perceived measurement errors that would notbe seen in a true PCB application. While these can seemlike functionality problems with the device output or otherdownstream circuitry, these errors can be minimized withproper setup techniques. Keeping scope leads, signal leads,and power leads perpendicular to high current traces and awayfrom switching circuitry, as well as keeping signal pins isolatedfrom primary pins, which may cause VCC to chop, will helpmitigate these problems.


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