AHV85110: Self-Powered Single-Channel Isolated GaNFET Gate Driver with Power-Thru Integrated Isolated Bias Supply

Description

The AHV85110 isolated gate driver is optimized for driving GaNFETs in multiple applications and topologies. An isolated output bias supply is integrated into the driver device, eliminating the need for any external gate drive auxiliary bias supply or high-side bootstrap. This greatly simplifies the system design and reduces EMI through reduced total common-mode (CM) capacitance. It also allows the driving of a floating switch in any location in a switching power topology.

The driver has fast propagation delay and high peak source/ sink capability to efficiently drive GaNFETs in high-frequency designs. High CMTI combined with isolated outputs for both bias power and drive make it ideal in applications requiring isolation, level-shifting, or ground separation for noise immunity.

Top Features

  • Power-Thru integrated isolated bias
    • No high-side bootstrap
    • No external secondary-side bias
  • 50 ns propagation delay, with excellent device-to-device
    matching of 5 ns
  • Separate drive output pins: pull-up (2.8 Ω) and pull-down
    (1.0 Ω)
  • Supply voltage 10.5 V < VDRV < 13.2 V
  • Undervoltage lockout on primary VDRV and secondary VSEC

Applications

  • AC-DC and DC-DC converters – totem-pole PFC, Half-/Full-Bridge, LLC, SR Drive, multi-level converters, phase-shifted full-bridge, etc.
  • Automotive – OBC, Traction Drive
  • Industrial – Transportation, Robotics
  • Grid Infrastructure – Micro-Inverters, solar

Part Number Specifications and Availability

Part Number Package Type Temperature RoHS
Compliant
Part Composition /
RoHS Data
Comments Samples Check Stock
AHV85110KNHTR 12-lead n/a -40°C to 125°C -- View Data New Contact your
local sales rep
Check
Distributor Stock

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Isolated ganfet Gate Driver - NH Packaging Image

Packaging

The device is available in a 12-pin, low-profile surface-mount NH package. It measures 10 mm × 7.66 mm × 2.53 mm. Several protection features are integrated, including undervoltage lockout on primary and secondary bias rails, internal pull-down on IN pin and OUTPD pin, fast response enable input, and OUT pulse synchronization with first IN rising edge after enable (avoids asynchronous runt pulses).